1. Field of the Invention
This invention relates to a DLL (Delay Locked Loop) circuit and a semiconductor device including the same. More particularly, it relates to a DLL circuit capable of performing a fast clocking operation, and a semiconductor device including the same.
2. Description of Related Art
A DLL (Delay Locked Loop) circuit, used as a clock generation circuit in a DRAM (Dynamic Random-Access Memory), variably controls a delay value of an input clock to generate a clock having a desired phase. A DLL circuit, provided with a DCC (Duty Correction Circuit), creates a waveform of an internal signal of, for example, the duty of 50%, without dependency upon the duty of the external clock. The duty, also termed a duty ratio, means the ratio of a HIGH level period with respect to one cycle.
With the increase of the operation frequency, the duty gets collapsed. The adverse effect of duty collapsing may be canceled to some extent by exercising control of delivering a DLL output to a pseudo output circuit (replica), feeding back an output signal of the pseudo output circuit and comparing the phase of the output signal to that of the clock CK. However, the pseudo output circuit (replica) cannot always make the cancellation optimum in light of the properties of interconnects and signals.
Patent Document 1, for example, discloses a configuration in a DLL in which the duty of an input clock is brought into coincidence with the duty of an output clock by providing a clock duty detection and correction circuit (CDC) on a succeeding stage of a variable delay circuit (VDL). In this configuration, the delay value of the variable delay circuit (VDL) is controlled by a rising edge of the clock. The phase of the rising edge is brought into coincidence with that of a reference input clock on a path of the variable delay circuit composed of a replica, a frequency dividing circuit, a PD (Phase Detector), CP1 (Charge Pump) and a bias. When the phase of the clock rising edge has been brought into coincidence with that of the reference input clock, the duty of the output clock is brought into coincidence with the duty of the reference clock by adjusting the pulse width of the output clock by the falling edge on the path of the duty detection and correction circuit (CDC) including the replica, a PFD (Phase Frequency Comparator) and CP2 (Charge Pump). Control is exercised so that the duty of the output clock is moved towards 50% from start of the operation of the DLL circuit until the rising edge of the output clock is phase-locked, and so that the duty of the output clock is caused to be coincident with that of the external clock after the timing the rising edge of the output clock has been locked into coincidence with the external clock. Hence, the duty of the output clock is changed from 50% to the duty of the input clock.
Patent Document 2 also shows a related technique.    [Patent Document 1]
JP Patent Kokai Publication No. JP2002-42469A, corresponding to U.S. Pat. No. 6,703,879 (FIGS. 1 and 14)    [Patent Document 2]
JP Patent Kokai Publication No. JP2003-91331 A, corresponding to U.S. Pat. No. 6,674,3149 (FIG. 1)
The entire disclosers of Patent Documents 1 and 2 are incorporated herein by reference thereto.